Mentor Graphics Augments its Analog/Mixed-Signal SoC Design Flow with ICassemble for Floorplanning and Automated Routing at All Levels of the Design Hierarchy
WILSONVILLE, Ore.--(BUSINESS WIRE)--July 7, 2003--Mentor Graphics
Corporation (Nasdaq: MENT) today announced the addition of ICassemble
to Mentor's analog/mixed-signal (AMS) system-on-chip (SoC) design
flow. ICassemble offers top-down floorplanning, advanced interactive
and automatic routing, and chip assembly capabilities within the
Mentor Graphics(R) IC Station(R) full-custom layout environment.
ICassemble is built into the IC Station tool -- with a common database
and integrated user interface -- allowing SoC designers to plan,
implement and connect blocks within a physical layout environment,
eliminating the need for time-consuming and error-prone data
abstractions and conversions. By using ICassemble's automated and
correct-by-construction capabilities in combination with the IC
Station product's custom editing tools, designers can gain significant
productivity benefits while achieving custom-quality layout for
today's complex mixed-signal designs.
"We've been witnessing a dramatic increase in the complexity of
our designs over the last few years," said Ludger Krucke, vice
president of the design department at ELMOS Semiconductor AG, one of
Europe's leading ASIC manufacturers. "ICassemble has been a powerful
and much-needed addition to our design flow, giving our designers the
ability to significantly decrease the time required to stitch together
analog and digital blocks on our chips. On one design, an automotive
controller chip with hundreds of top-level nets, we successfully
reduced the routing and assembly time by a factor of four."
Automating Mixed-Signal Chip Planning
Currently, the majority of mixed-signal chip planning is done by
hand, a slow and laborious process that can lead to design errors and
numerous iterations. During final assembly, the completed blocks are
also placed and routed manually without aid of design-rule-correct
automation.
ICassemble is the only tool that addresses these problems with
three powerful technologies, all integrated within a full custom
layout environment: a schematic- and netlist-driven floorplanner,
IRoute, an auto-interactive router, and ARoute, an automatic, gridless
shape-based router. All three components work off a unified set of
design constraints that can be manipulated to control aspects such as
pin placement, wiring, timing, shielding and signal integrity to
achieve design-rule-correct layouts.
Floorplanner
The ICassemble floorplanner facilitates top-down chip planning
based on global connectivity and design constraints to speed design
closure. Upon establishing hierarchical connectivity from disparate
sources such as schematics and/or netlists, designers can partition
the chip, estimate block sizes, and then place the blocks and assign
pin locations so as to minimize congestion and wire lengths of
critical signals.
IRoute
IRoute is an interactive router to speed up signal routing at any
level of hierarchy. In the early chip planning stage, IRoute can
rapidly route power buses and critical signals to meet timing
constraints. At the block level, IRoute can automate point-to-point
connections, buses and mirrored routes. During engineering change
orders (ECOs), IRoute can quickly fix changes by intelligently pushing
and shoving circuitry out of the way to complete connections. In all
cases, IRoute's inherent adherence to constraints on shielding,
spacing, widths, and directions of wires, along with its ability to
look up and the down the hierarchy guarantees correct-by-construction
results.
ARoute
ARoute is an iterative rip-up and re-route tool that allows bulk
routing of nets, selected by region or group, to rapidly complete chip
assembly in a fraction of the time required for manual routing.
ARoute's N-layer and shape-based technology makes it suitable at all
levels of hierarchy, from the device to the full chip. Its layouts
meet DRC rules since it is able to recognize and avoid blockages both
in sub-blocks and at higher levels. By placing appropriate constraints
on wire spacing, widths, and shielding it can be driven to produce
results that meet signal integrity requirements.
"The increase in analog content on SoC designs is forcing more
layout teams to merge digital and analog blocks on a single chip,"
said Jue-Hsien Chern, vice president and general manager, deep
submicron division, Mentor Graphics. "There is no other solution in
the market today that provides ICassemble's top-down planning and
routing capability integrated within a full-custom layout design
tool."
Pricing and Availability
The ICassemble tool is priced at $75,000 and is available today on
Linux, Sun Solaris and HP-UX operating systems. More information is
available at www.mentor.com/cicd/icassemble.html or by calling
1-800-547-3000.
Mentor Graphics Integrated AMS SoC Design Tools
Mentor Graphics delivers superior technology for AMS SoC design,
from capture and simulation through physical implementation,
verification and analysis. The tool set includes the Design
Architect(R) IC product, with a powerful AMS SoC design cockpit, and
the IC Station chip assembly solution for physical layout, top-level
floor planning and routing. The ADVance MSTM tool is a single-kernel,
language-independent simulation environment for digital, analog,
mixed-signal and RF circuits. The Calibre(R) and Calibre xRC(TM) tools
deliver the industry's highest capacity, performance and accuracy for
physical verification and parasitic extraction. This fully integrated
set of tools is available immediately for Linux, HP and Sun platforms.
About Mentor Graphics Corporation
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of about
$600 million and employs approximately 3,500 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: www.mentor.com.
Mentor Graphics, IC Station, Design Architect and Calibre are
registered trademarks and Advance MS and Calibre xRC are trademarks of
Mentor Graphics Corporation. All other company or product names are
the registered trademarks or trademarks of their respective owners.
CONTACT: Mentor Graphics
Matthew Franklin, 503/685-1077
matthew_franklin@mentor.com
or
Weber Shandwick
Kara Udziela, 503/552-3731
kudziela@webershandwick.com
